1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device of which the operating speed is increased by stress application, and to a process of manufacturing the same.
2. Description of the Related Art
With the development of microfabrication technology, nowadays it is possible to fabricate an ultrafine and ultra-high speed semiconductor device having a gate length of less than 100 nm.
In such an ultrafine and ultra-high speed transistor, the effect of simple reduction in process feature sizes is significantly smaller than before. Meanwhile, the mobility of electrons or holes that travel in the channel region is greatly influenced by stress applied to the channel region. Many attempts have been made to improve the operating speed of semiconductor devices by optimizing the stress applied to the channel region, which has become much smaller compared with earlier semiconductor devices. Relevant technologies are disclosed in Japanese Laid-Open Patent Application No. 2003-234455 and Japanese Patent No. 2718767, for example.
FIGS. 1A and 1B show ideal stress distributions for achieving improved operating speed in an n-channel MOS transistor and a p-channel MOS transistor, respectively, according to Ota, K. et al., 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 138-139.
With reference to FIG. 1A, in the n-channel MOS transistor, an n-type polysilicon gate electrode 3N is formed across a device region 1N. Thus, the device region 1N is divided by the polysilicon gate electrode 3N into an n-type source region S and an n-type drain region D.
Similarly, in the p-type MOS transistor shown in FIG. 1B, a p-type polysilicon gate electrode 3P is formed across a device region 1P, so that the device region 1P is divided into a p-type source region S and a p-type drain region D.
In the n-channel MOS transistor shown in FIG. 1A, when a tensile stress is applied in the gate width direction and the gate length direction (in-plane tensile stress), the mobility of electrons in the channel region immediately below the gate electrode 3N increases, whereby increased transistor operating speed is achieved. On the other hand, in the p-channel MOS transistor shown in FIG. 1B, when a tensile stress is applied in the gate width direction and a compressive stress is applied in the gate length direction (uniaxial compressive stress), the mobility of holes in the channel region immediately below the gate electrode 3P increases, whereby improved transistor operating speed can be obtained.
FIG. 2A shows a proposed structure for inducing the tensile stress immediately below the channel region of an n-channel MOS transistor in the gate length direction, as in FIG. 1A.
With reference to FIG. 2A, in a device region 1N defined on a silicon substrate 1, an n+ polysilicon gate electrode 3N is formed via a gate insulating film 2N. In the silicon substrate 1, an n-type source extension region 1aN and an n-type drain extension region 1bN are formed on either side of the polysilicon gate electrode 3N within the device region 1N.
On either sidewall surface of the gate electrode 3N, sidewall insulating films 4nN consisting of SiN films are formed via sidewall oxide films 4oN. An n+ source region 1cN and an n+ drain region 1dN are formed in the silicon substrate 1 outside the sidewall insulating films 4nN within the device region 1N.
Over the n+ source region 1cN, the drain region 1dN, and the n+ gate electrode 3N, there are formed silicide films 5SN, 5DN, and 5GN, respectively. Over the silicon substrate 1, an SiN film 6N with a stored tensile stress is formed in such a manner as to continuously cover the silicide films 5SN, 5DN, and 5GN and the sidewall insulating films 4nN.
Due to the tensile stress in the SiN film 6N, the gate electrode 5GN is biased toward the silicon substrate 1 vertically with respect to the substrate surface. As a result, in the channel region immediately below the gate electrode 3N, there is induced a strain similar to the strain that results when the tensile stress is applied in the gate length direction in FIG. 1A.
FIG. 2B shows a proposed structure for inducing a compressive stress immediately below the channel region that acts in the gate length direction in a p-channel MOS transistor, as in FIG. 1B, according to Pidin, S., et al., IEDM Tech. Dig., p. 213, 2004.
With reference to FIG. 2B, in a device region 1P defined on a silicon substrate 1, a p+ polysilicon gate electrode 3P is formed via a gate insulating film 2P. In the silicon substrate 1, a p-type source extension region 1aP and an p-type drain extension region 1bP are formed on either side of the polysilicon gate electrode 3P within the device region 1P.
On either sidewall surface of the gate electrode 3P, sidewall insulating films 4nP consisting of SiN films are formed via sidewall oxide films 4oP. In the silicon substrate 1, a p+ source region 1cP and a p+ drain region 1dP are formed outside the sidewall insulating films 4nP within the device region 1P.
Over the p+ source region 1cP, the drain region 1dP, and the p+ gate electrode 3P, silicide films 5SP, 5DP, and 5GP are formed, respectively. Further, over the silicon substrate 1, an SiN film 6P with a stored compressive stress is formed in such a manner as to continuously cover the silicide films 5SP, 5DP, and 5GP and the sidewall insulating films 4nP.
Due to the compressive stress in the SiN film 6P, the gate electrode 3P is biased away from the silicon substrate 1 vertically with respect to the substrate surface. As a result, in the channel region immediately below the gate electrode 3P, there is induced a strain similar to the strain that results when the compressive stress is applied in the gate length direction in FIG. 1B.
However, when such an n-channel MOS transistor and a p-channel MOS transistor are to be formed on the same substrate in order to form a CMOS device, for example, using the structures shown in FIGS. 2A and 2B, it becomes necessary to form the tensile stress film 6N and the compressive stress film 6P separately, thereby requiring complex production steps.
Furthermore, in a strained semiconductor device manufactured according to a conventional process, the pattern and size of stress that can be applied to the channel region is determined by the semiconductor device manufacturing process, and the stress distribution cannot be changed freely after the manufacture of the semiconductor device.